Sr. Principal DSP Architect (Optical Transceivers & PAM4)

Astera Labs•San Jose, CA

7d•$210,000 - $260,000

About The Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview As a Sr. Principal DSP Architect, you will be the technical visionary leading the definition and development of next-generation Digital Signal Processing (DSP) architectures. Your focus will be on high-speed PAM4 (Pulse Amplitude Modulation 4-level) systems and coherent/direct-detect optical transceivers. You will bridge the gap between theoretical communications theory and silicon implementation, driving the roadmap for 800G, 1.6T, and beyond.

Requirements

Education: PhD or MS in Electrical Engineering, Communication Theory, or a related field.
Experience: 12+ years of experience in DSP design, specifically for high-speed SerDes or optical communications.
Technical Deep Dive: Expertise in PAM4 signaling and the associated challenges (non-linearity, SNR requirements).
Deep understanding of Digital Filter Design (FIR, IIR) and adaptive signal processing.
Experience with high-speed ADC/DAC architectures and their impact on DSP performance.
Tooling: Proficiency in MATLAB/Simulink, Python (NumPy/SciPy), and SystemC.
Silicon Success: A proven track record of taking complex DSP architectures from concept through tape-out to high-volume production.

Nice To Haves

Experience with Coherent Optical technologies (QAM, polarization multiplexing).
Knowledge of Machine Learning applications in DSP for non-linearity compensation.
Familiarity with hardware description languages (Verilog/SystemVerilog) and the synthesis flow

Responsibilities

Architectural Leadership: Lead the definition of DSP micro-architecture for high-performance ASICs, focusing on low-power, high-throughput data paths.
Algorithm Development: Design, model, and simulate advanced DSP algorithms for: Adaptive Equalization (FFE, DFE, MLSE). Forward Error Correction (FEC). Clock and Data Recovery (CDR). Chromatic Dispersion (CD) and Polarization Mode Dispersion (PMD) compensation.
Modeling & Simulation: Develop bit-accurate and performance-accurate models using Python, MATLAB, or C++ to validate architectural choices against Bit Error Rate (BER) targets.
Cross-Functional Collaboration: Work closely with Analog Mixed-Signal (AMS) designers to optimize the ADC/DAC interface and with RTL teams to ensure power-efficient hardware implementation.
Performance Trade-offs: Conduct rigorous Power, Performance, and Area (PPA) analysis to balance complex DSP requirements with the thermal and size constraints of optical modules (e.g., QSFP-DD, OSFP).
Standards Contribution: Represent the company in industry standards bodies (IEEE 802.3, OIF) to influence future optical communications protocols.

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