ASIC Design Engineer

Ralliant • Beaverton, OR

5d • $81,500 - $151,300 • Onsite

About The Position

We are seeking a highly skilled individual to join our Tektronix design center in Beaverton, Oregon. In this role, you will be responsible for designing cutting-edge CMOS, BiCMOS, and HBT RF integrated circuits that form the core of our next-generation products. You will collaborate closely with a team of exceptional engineers and managers to lead the development of industry-leading solutions using state-of-the-art design tools.

Requirements

• MSEE/PhD in Electrical Engineering or equivalent.
• direct experience in designing analog and/or mixed signal integrated circuits for analog signal processing (e.g., amplifiers, samplers, PLLs, ADCs, DACs).
• Proficient in using modern ASIC design tools.
• Strong verbal communication skills with the ability to generate high-quality documentation.
• Willingness to undertake some domestic travel as required.
• Experience in layout design for critical cells.
• Prior experience working effectively with remote domestic teams.
• A strong drive to stay updated with process technology advancements and a commitment to continuous learning and improvement.
• Ability to comprehend and influence architectural or design decisions.

Responsibilities

• Design: Develop and manage analog and mixed signal blocks.
• Layout Design: Design sensitive layouts and assist in layout floor planning.
• Simulation and Optimization: Run simulations on designs to optimize performance and manufacturability.
• Signal Analysis: Perform signal analysis on systems external to the ASIC.
• Characterization: Characterize designs or generate comprehensive characterization plans.
• System-Level Analysis: Collaborate with instrument product line architects to analyze power, cost, and performance trade-offs at the system level, driving informed decision-making.
• Design Reviews: Present design reviews to peers to ensure the quality and integrity of designs.
• Project Management: Work with Program Managers and Functional Managers to maintain project schedules and facilitate communication across teams.
• Process Improvement: Contribute to the enhancement of ASIC design processes to improve communication and efficiency within the group.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: Ph.D. or professional degree