CPU Core Timing and Automation Engineer

Intel Corporation • Folsom, CA

2d • Hybrid

About The Position

Do Something Wonderful! Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Who We Are The Full Chip Timing (FCT) Design Automation team plays a critical role in supporting all aspects of full chip timing integration. Our mission is to enable seamless timing closure and optimization across the entire backend flow. We develop and maintain automation environments, tools, and methodologies that ensure high-quality timing models and constraint management. Who You Are Some of the responsibilities of this role will include but not limited to: Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs. Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks. Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently with strong scripting expertise. Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on product plans such as operating conditions and binning. Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning and rollup generation, producing indicators for the team. Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines. Build and maintain automation environments for timing model generation. Run timing models and generate and publish indicators. Support backend platforms to resolve timing violations• Drive timing closure across physical design stages Innovate with AI-based tools, indicators, and ad-hoc automation Own constraint management and budgeting flows using top high end CAD tools Proactive, self-driven mindset with strong ownership attitude Customer-focused and collaborative team player Curious, innovative, and eager to push boundaries

Requirements

• You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position.
• The candidate must have a Bachelor’s Degree in Electronics, Electrical, Computer Engineering or a related field with relevant experience with 1+ years of experience in scripting and software development (TCL, Python, AI-based coding tools) -OR- Master’s Degree in Electronics/Electrical/Computer Engineering
• At least a year of experience in backend design: synthesis, place and route (P and R)
• At least a year of experience with optimization flows of STA tools

Nice To Haves

• 2+ years of experience in: x86 CPU architecture
• TCL/Perl/Python programming

Responsibilities

• Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs.
• Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks.
• Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently with strong scripting expertise.
• Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on product plans such as operating conditions and binning.
• Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning and rollup generation, producing indicators for the team.
• Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.
• Build and maintain automation environments for timing model generation.
• Run timing models and generate and publish indicators.
• Support backend platforms to resolve timing violations
• Drive timing closure across physical design stages Innovate with AI-based tools, indicators, and ad-hoc automation Own constraint management and budgeting flows using top high end CAD tools
• Proactive, self-driven mindset with strong ownership attitude
• Customer-focused and collaborative team player
• Curious, innovative, and eager to push boundaries

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level