Design Verification Engineer

Meta•Sunnyvale, CA

About The Position

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.

Requirements

Requires Master’s degree (or foreign equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or related field
Requires completion of a university-level course, research project, thesis, or internship involving the following:
Hardware verification, with hands-on experience in SystemVerilog, C, C++, and scripting languages such as Python, TCL, Perl, and Shell
Implementing UVM or comparable verification methodologies
EDA tools relevant to digital design verification, simulation, and debug
Analytical skills for solving complex technical problems and ensuring robust and reliable silicon solutions
Eligibility and ongoing authorization to work in the country of employment
Demonstrated ability to collaborate effectively within multidisciplinary engineering environments

Responsibilities

Collaborates with researchers, architects, and designers to establish comprehensive verification strategies for a variety of core IP blocks and complex System-on-Chip (SoC) solutions.
Participates in creating and maintaining test bench requirements and detailed test cases for state-of-the-art hardware modules.
Utilizes industry-standard hardware verification methodologies—such as Universal Verification Methodology (UVM)—for the creation of robust testbenches.
Employs languages including SystemVerilog, C, and C++ for digital design verification and development of verification infrastructure.
Works extensively with Electronic Design Automation (EDA) tools to perform simulation, debugging, and analysis of hardware designs.
Develops automation scripts in Python, TCL, Perl, and Shell to streamline verification flows and enhance test coverage.
Drives the execution of detailed test plans, tracks verification progress through clearly defined metrics (functional and code coverage), and ensures closure of verification cycles prior to tape-out.
Leads debugging efforts, identifies root causes of functional failures, and partners with design teams to implement resolutions.
Engages in cross-functional collaboration with teams spanning design, modeling, emulation, and silicon validation in order to guarantee the delivery of high-quality silicon.
Demonstrates strong interpersonal and collaborative skills to achieve shared engineering goals.
Leads and participates in ongoing enhancements of verification methodologies and best practices, leveraging the latest advancements in verification tools and industry technologies.