Principal Design Engineer

Micron • San Jose, CA

1d

About The Position

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Principal Design Engineer in Micron’s NVEG organization, you will be at the forefront of shaping the future of memory technology! In this role, you will lead the development, layout, and optimization of ground breaking datapath circuits for next-generation NAND flash memory. You will act as a key technical leader, driving task forces and making strategic architectural decisions to achieve critical design targets such as unprecedented data rates and lower power consumption. By evaluating the trade-offs of emerging architectures, you will advise end-to-end implementation—from design planning and layout to silicon validation—ensuring project achievements are met while mentoring the next generation of engineering talent! What’s Encouraged Daily: Technical Ownership: Manage, design, and verify major IO/datapath blocks (e.g., input receiver, serializer, deserializer, clock distribution, equalizer, ZQ calibration, ONFI training features, and wave pipelines) to strictly meet performance specifications. Layout & Optimization: Model layout parasitics and optimize signal quality. Conduct regular layout reviews to identify and complete opportunities for area reduction and power efficiency improvements. Multi-functional Integration: Collaborate closely with project integration and other functional design teams to define and negotiate specifications for major block interfaces. Silicon Bring-up & Yield: Partner with Product Engineering (PE) to define silicon experiments, drive silicon debugging, and propose architectural fixes to improve yield and performance. Customer & Systems Alignment: Liaise with Applications Engineering (Apps) to evaluate the feasibility of introducing new specifications, balancing customer needs against design requirements and physical limitations. Document methodologies clearly. Present final results to expert panels and team members. Actively mentor engineers newer to the field to improve the team's technical skills.

Requirements

• BS or MS in Electrical Engineering, or a related filed with 8+ years of relevant IC design experience
• 10+ years of in depth knowledge and deep intuitive understanding of high-speed IO circuit performance, power/area optimization, and top level chip architecture/floorplanning.
• Proven track record in physical design flows, layout optimization, and parasitic extraction.
• Demonstrated experience with high-speed interfaces for NAND and sophisticated training/calibration features.
• Strong project management skills with the ability to lead sophisticated design initiatives and effectively communicate progress and outcomes to diverse team members.

Nice To Haves

• Hands-on experience in applying AI to improve design quality, workflow efficiency, or layout optimization.
• Experience with DRAM interface(e.g. DDR4/5, LPDDR5/6, HBM3/3E/4) or other high speed industry standard interfaces.
• Experience with signal/power integrity (SI/PI) and chip-level power delivery network(PDN) design and optimization
• Comprehensive understanding of sophisticated CMOS device physics, device reliability mechanisms, BSIM modeling, and CMOS targets for high-speed IO operation.

Responsibilities

• Manage, design, and verify major IO/datapath blocks (e.g., input receiver, serializer, deserializer, clock distribution, equalizer, ZQ calibration, ONFI training features, and wave pipelines) to strictly meet performance specifications.
• Model layout parasitics and optimize signal quality.
• Conduct regular layout reviews to identify and complete opportunities for area reduction and power efficiency improvements.
• Collaborate closely with project integration and other functional design teams to define and negotiate specifications for major block interfaces.
• Partner with Product Engineering (PE) to define silicon experiments, drive silicon debugging, and propose architectural fixes to improve yield and performance.
• Liaise with Applications Engineering (Apps) to evaluate the feasibility of introducing new specifications, balancing customer needs against design requirements and physical limitations.
• Document methodologies clearly.
• Present final results to expert panels and team members.
• Actively mentor engineers newer to the field to improve the team's technical skills.

Benefits

• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Number of Employees: 5,001-10,000 employees