Principal Logic Circuit Design Engineer

Micron Technology • Folsom, CA

5d

About The Position

Define, architect, and lead the development of advanced RTL blocks for HBM subsystems, ensuring alignment with product requirements and architectural goals. Own end‑to‑end front‑end design, including micro‑architecture, RTL development, simulation strategy, and design quality. Drive technical decisions across circuit development, synthesis, constraints, and physical‑design integration, ensuring timing, power, and area compliance. Guide and review global engineering teams, providing technical leadership across multiple projects and functional areas. Champion design methodologies, develop reusable frameworks, and improve RTL design flows, validation strategies, and sign‑off processes. Collaborate closely with physical design, verification, architecture, and product engineering to integrate subsystems and deliver high‑quality silicon. Lead root‑cause analysis and corrective actions for complex design issues, ensuring long-term design robustness. Communicate effectively at all levels, contributing to technical planning, project execution, and cross-organizational alignment.

Requirements

• Bachelor's degree with 9+ years, or Master's degree with 7+ years of proven experience in digital design and RTL development
• Expert-level knowledge of front‑end digital design, RTL coding, micro‑architecture, and system integration
• Deep understanding of timing closure, power optimization, area trade-offs, and system-level complexity management
• Strong experience with synthesis, STA, constraints, LEC, Lint, CDC, and front‑end sign‑off methodologies
• Proven ability to lead technical teams, mentor engineers, and influence design direction across large programs
• Exceptional problem-solving, analytical, communication, and technical leadership skills

Nice To Haves

• Experience with UPF, power‑intent development, power analysis, DFT/scan insertion, ATPG, and timing model generation
• Proficiency in Python, Perl, or scripting to automate and enhance design flows
• Familiarity with sophisticated place-and-route tools and back‑end requirements for successful RTL-to-GDS integration
• Proven history delivering high‑complexity systems, preferably in memory, high‑speed I/O, or compute‑intensive ASIC designs
• Ability to define architectural trade-offs, influence product direction, and guide teams toward scalable and maintainable design solutions

Responsibilities

• Define, architect, and lead the development of advanced RTL blocks for HBM subsystems
• Own end‑to‑end front‑end design, including micro‑architecture, RTL development, simulation strategy, and design quality
• Drive technical decisions across circuit development, synthesis, constraints, and physical‑design integration
• Guide and review global engineering teams, providing technical leadership across multiple projects and functional areas
• Champion design methodologies, develop reusable frameworks, and improve RTL design flows, validation strategies, and sign‑off processes
• Collaborate closely with physical design, verification, architecture, and product engineering to integrate subsystems and deliver high‑quality silicon
• Lead root‑cause analysis and corrective actions for complex design issues
• Communicate effectively at all levels, contributing to technical planning, project execution, and cross-organizational alignment

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level