Principal Physical Design Engineer, HBM

Micron Technology • Richardson, TX

6d

About The Position

Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Requirements

• Bachelor’s degree or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent professional experience.
• 12+ years of hands‑on experience in advanced‑node physical design with proven tape‑out experience in HBM, dynamic random‑access memory (DRAM), or large memory‑centric designs.
• Deep expertise in floorplanning, hierarchical physical design, timing closure, static timing analysis, power integrity (IR/EM), thermal analysis, and physical signoff.
• Expert‑level experience with Cadence Innovus and/or Synopsys ICC2 or Fusion Compiler, plus experience with Voltus, RedHawk, or equivalent power integrity tools.
• Familiarity with Calibre design rule checking, layout versus schematic, and advanced foundry signoff flows.

Nice To Haves

• Experience with HBM2E, HBM3, or HBM3E products and TSV‑based designs, including micro‑bump layouts.
• Knowledge of die‑to‑die interfaces, wide parallel buses, and advanced packaging such as 2.5D interposers and chiplets.
• Background in signal integrity considerations for dense, high‑speed memory designs.
• Strong Tcl or Python scripting skills for physical design flow automation.
• Experience supporting system‑level integration with graphics processing units, accelerators, or system‑on‑chips.

Responsibilities

• Lead end‑to‑end physical design for High Bandwidth Memory (HBM) base and memory dies from netlist through GDSII, including floorplanning, power planning, placement, clock tree synthesis, routing, and signoff.
• Define and drive HBM‑specific physical architecture, including channel partitioning, physical layer (PHY) placement, through‑silicon via (TSV) keep‑out regions, and die‑package co‑design alignment.
• Optimize bandwidth, latency, power, and yield through architecture‑level tradeoffs and collaboration with memory architecture, PHY, RTL, synthesis, design‑for‑test, and packaging teams.
• Lead power delivery network design and ensure IR drop, electromigration, and thermal closure across all operating modes.
• Oversee timing closure across corners for high‑speed logic and HBM PHY interfaces, addressing signal integrity, noise, and crosstalk.
• Ensure physical signoff readiness, including static timing analysis, IR/EM, signal integrity, design rule checks, layout versus schematic, density, and reliability compliance.
• Drive engineering change order strategies, flow improvements, automation, and methodology development for HBM physical design.
• Mentor engineers and serve as a key technical voice in tape‑out and executive design reviews.

Benefits

• Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.
• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.
• For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal