Process Technology Design Engineer

Intel • Hillsboro, OR

10h • Hybrid

About The Position

This position is with the Library Benchmarking team within Intel Foundry's Advanced Design Library organization. This group works closely with both process and product design teams, to deliver capabilities to optimize and integrate digital-logic circuits with Intel's leading edge process technology. The successful Candidate will participate in design, development, and analysis of pre-silicon and post-silicon "technology benchmarking metrics." These metrics are used to target and benchmark digital-logic power and performance associated with the various technology nodes. The candidate is also expected to analyze power/performance tradeoffs between the different Standard Cell library offerings during technology pathfinding. Responsibilities include, but are not limited to: Participating in Technology and Standard Cell library architecture pathfinding activities. Contributing to Design Technology Co-optimization (DTCO) of different Standard Cell library offerings on a given technology node. Design and development of pre-silicon and post- silicon technology benchmarking metrics. Design and characterization of process monitoring oscillators followed by Post-silicon analysis, to identify and quantify FEOL/BEOL factors contributing to Silicon-to-Simulation gap. Strong customer orientation, excellent written and verbal communication skills, and ability to work with external and internal partners in a flexible manner are expected.

Requirements

• You must possess the minimum qualifications to be initially considered for this position.
• Master’s degree in Electrical/Computer Engineering with 2+ years of experience – OR – PhD degree in Electrical/Computer Engineering
• Technical background in the areas of CMOS device electronics and digital-logic/mixed-signal circuits.
• Strong customer orientation, excellent written and verbal communication skills, and ability to work with external and internal partners in a flexible manner are expected.

Nice To Haves

• Experience using CAD tools in one or more of the following areas: circuit simulation and modeling, physical layout design, design validation, field solver simulation, design synthesis and APR.
• Strong capability of one or more languages (C/C++, TCL, Perl, Python) for design automation.
• JMP analysis skills.
• 2-4 years of working in an industrial environment

Responsibilities

• Participating in Technology and Standard Cell library architecture pathfinding activities.
• Contributing to Design Technology Co-optimization (DTCO) of different Standard Cell library offerings on a given technology node.
• Design and development of pre-silicon and post- silicon technology benchmarking metrics.
• Design and characterization of process monitoring oscillators followed by Post-silicon analysis, to identify and quantify FEOL/BEOL factors contributing to Silicon-to-Simulation gap.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel .
• Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
• The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
• Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
• Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level