SoC Product Architect Low Power SoC

NVIDIA•Seattle, CA

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are looking for a senior SoC/Product Architect to define and drive the architecture of next-generation low-power SoCs at NVIDIA. You will own concept-to-product architecture decisions — balancing power, performance, and area — while partnering across CPU, GPU, memory, and IO teams to resolve system-level trade-offs and acting as the technical interface for product requirements and customer feedback.

Requirements

12+ years in SoC or product architecture, with deep hands-on knowledge of CPU, GPU, memory, and low-power IO subsystems
Master's Degree in Computer Engineering or Electrical Engineering (or equivalent experience)
Strong understanding of SoC architecture for low power mobile devices, including DVFS, power domains, and retention strategies
Experience with DL inference at the edge (TensorRT, TFLite, ONNX) and mapping workloads to constrained hardware
Track record of driving architecture decisions across multi-functional teams in a large organization

Responsibilities

Define SoC architecture for low-power platforms — CPU, GPU, memory subsystem, low-power IOs, and power management
Drive concept-level PPA trade-off analysis and lead the power/performance budget across the SoC
Architect the memory subsystem (LPDDR5/6, on-chip SRAM, bandwidth, QoS) for constrained power envelopes
Work with DL teams for evaluating and crafting workloads for low power — mapping tasks to constrained hardware; define optimization opportunities in partnership with Nvidia’s DL team.
Partner with CPU, GPU, and IO architecture teams inside NVIDIA to align on shared IPs and integration strategies
Translate customer requirements into architectural constraints; drive PRD development and requirements triage
Engage directly with customers pre-silicon to collect feedback and follow through on product decisions