ASIC DFT Engineer

Broadcom • San Jose, CA

1d

About The Position

Broadcom is seeking candidates for a Staff DFT engineer position. The successful candidate will be responsible for developing and implementing DFx (Design for Test/debug & manufacturability) solutions for Digital, mixed signal IPs. Candidate will also drive/push state of the art in the areas of testability, debug to enable low DPPM DFx solutions while optimizing the cost for test.

Requirements

• Knowledge of Testability techniques and features (SCAN, Built-in-Self-Tests, boundary scan.) covering digital logic, embedded memories and Serdes PHY/IO’s
• Scan architectural trade-off, coverage analysis, ATPG pattern generation and verification
• Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms
• Well versed in JTAG standards (1149.1 and 1149.6, 1687) and boundary scan
• Strong Pre/Post Silicon debugging, analytical and independent problem solving ability
• Strong knowledge of digital design and logical equivalence checking
• Experience with Gate level simulations and debug with industry simulator tools
• Experience in developing STA constraints for DFT logic/modes and working knowledge of primetime
• Post silicon experience on pattern bring-up, debug and silicon characterization etc
• Working knowledge of TCL, perl and shell scripting
• Hands on experience with Mentor/Siemens DFT Tessent tool suite for DFT insertion is desirable
• Working knowledge of SERDES, Analog /mixed-signal DFT solutions (like IOBIST, AC boundary scan) is a plus
• Must be a team player with good verbal and written communication skills.
• Must be a self-driven engineer with good planning and organizing skills to deliver high quality output in a timely manner.
• Bachelors in Electrical or Computer Science Engineering required with a minimum of 8+ years of relevant industry experience or a Master’s Degree with a minimum of 6+ years of relevant industry experience

Responsibilities

• Own IP DFT architecture, implementation, verification, signoff STA constraints for DFT
• Optimize DFT architecture for test cost, test power and physical design constraints
• Deliver optimal retargetable ATPG patterns for usage across business units
• Collaborate with front-end and backend engineers to implement optimal DFx solutions
• Support chip teams on IP DFT integration, pattern verification and ATE bring-up
• Participate in silicon bring-up, characterization, and yield recovery

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level