Memory Controller Design Engineer
About The Position
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. QCT Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high speed DDR Controllers. The front end of the DDR controller interfaces to the rest of the system such as CPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products. The candidate will work on architecture, design, and deployment of the Memory Controllers for the LPDDR/PCDDR technologies into QCT products. You will develop or contribute to the development of design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will also participate in C/C++ modeling of memory controller IP. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.
Requirements
- DDR controller architectures especially the front end interfacing to the CPU, DSP, and multimedia processors
- Experience with x86 or ARM CPU/bus architectures
- Bachelor's degree in Science, Engineering, or related field.
Responsibilities
- Develop or contribute to the development of design specifications
- Drive the micro-architecture of portions of the logic design
- Implement and deliver RTL and work with verification engineers to deliver high quality designs
- Responsible for debugging designs and also provide debug support when integrated into the rest of the chip
- Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis
- Participate in C/C++ modeling of memory controller IP
- Make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
